CoolRunner XPLA3

The CoolRunner™ XPLA3 (eXtended Programmable Logic Array) family of CPLDs is targeted for low power systems that include portable, handheld, and power-sensitive applications. Each member of the XPLA3 family includes Fast Zero Power (FZP) design technology that combines low power and high speed.

The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power-sensitive designs that require leading edge programmable logic solutions.

The XCR3384XL is a 3.3V, 384 macrocell CPLD targeted at power-sensitive designs that require leading edge programmable logic solutions.

The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at power-sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates.

The XCR3128XL is a 3.3V 128 macrocell CPLD targeted at power-sensitive designs that require leading edge programmable logic solutions. A total of eight function blocks provide 3,000 usable gates.

The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at power-sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates.

The XCR3032XL is a 3.3V, 32- CPLD targeted at power-sensitive designs that require leading edge programmable logic solutions. A total of two function blocks provide 750 usable gates.

This document describes the behavior of the I/Os under various operating conditions. It describes how to use the different termination modes, how to understand thresholds, and how loading affects the I/Os.

This document discusses thermal, electrical, moisture, and soldering characteristics of Xilinx® device packages.

Summary of the reliability test data and results for Xilinx devices updated four times per year.

CoolRunner™ XPLA3 CPLD Errata DS012-E10: Incorrect initialization under an obscure power condition.

Xilinx is changing the primary supplier for Ball Grid Array (BGA) shipping trays from Peak to both Daewon and Kostat.

Xilinx is changing from a 6 dot HIC to a 3 dot HIC to comply with industry standard dry packing requirements, JEDEC standard J-STD-033.

Updated availability dates: For XCR3032XL change from March 2005 to January 2005. For XCR3128XL change from December 2004 to January 2005.

PCN2003-10 announces a change in the wafer fabrication facility for the CoolRunner XCR3128XL

The purpose of this notice is to announce the addition of STATS ChipPAC in Singapore (SCS) as a qualified assembly partner for Plastic Quad Flat Pack (PQFP), Thin Quad Flat Pack (TQFP/VQFP), and Ball Grid Array in wire bond (BGA) packages.

Design File(s):

• Qualification Report for XCN06016

Xilinx is adding shipping trays produced by Kostat, Inc. for the new CS144/CSG144 and CS280/CSG280 Laminate packages.

A package substrate change for Chip Scale (Tape) and lead-free Chip Scale (Tape).

Design File(s):

• Qualification Report for XCN05018

This notification describes a material set consolidation of mold compound and die-attach epoxy across various packages in all Xilinx device families. The new material set is already used in Xilinx RoHS-compliant products. There is no change to the form, fit, or function of the devices.

Design File(s):

• Qualification Report for XCN05011

Xilinx is implementing a Warehouse Management System (WMS) in its internal warehouses worldwide. As a result, a license plate number (LPN), which is a unique tracking number, will now appear on labels beginning in August 2007. There are no changes to the form, fit, or function of the product.

Xilinx is discontinuing certain Spartan®, XC4000XL, CoolRunner™, and Programming Solution products.

To advice customers that Xilinx has added alternate shipping tray for 28mm x 28mm QFP packages and 31mm x 31mm BGA packages.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

To communicate that Xilinx is discontinuing Spartan®-XL FPGA, XC9500 In-System Programmable CPLD products, all Automotive IQ Family offerings of Spartan®-II FPGA products and CoolRunner™ XPLA3 CPLD products.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

This application note describes how to drive LEDs using Xilinx CPLDs.

Checklist application note giving best practice CPLD design methodology.

This introduction covers the basics of VHDL as applied to CPLDs. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language to extract the best performance from CPLD designs.

MP3 portable players are the trend in music-listening technology. These players do not include any mechanical movements, thereby making them ideal for listening to music during any type of activity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music in a lot less space than current CD technology. Software is readily available to create MP3 files from an existing CD, and the user can then download these files into a portable MP3 player to be enjoyed in almost any environment.

This application note provides a quick and simple method for estimating power consumption of CoolRunner™ XPLA3 CPLDs. As an alternative to XPower, power can be quickly and easily computed using the equation and coefficients provided in this application note.

The purpose of this application note is to investigate the PCI (Peripheral Component Interface) environment when using 5 volt tolerant, 3.3 volt supply integrated circuits. In particular, we will examine the meaning of the statement "PCI compliant" when used in CPLD or FPGA data sheets.

This application note describes power-up characteristics for CoolRunner™ CPLDs that may be of interest, depending upon where and how the devices are used.

Describes the bahavior of CPLDs during power up.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

This application note covers the basics of how to use Verilog as applied to Complex Programmable Logic Devices. Various combinational logic circuit examples, such as multiplexers, decoders, encoders, comparators, and adders are provided. Synchronous logic circuit examples, such as counters and state machines are also provided.

This document focuses on the design of a wireless transceiver using CoolRunner™ CPLDs. The wireless transceiver is implemented using the CoolRunner demo board. The wireless transceiver is the perfect application of the low-power capabilities of a CoolRunner CPLD.

This document describes the design implementation for controlling a Texas Instruments ADS7870 Analog to Digital Converter (ADC) in a Xilinx CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLD available and the ideal target device for controlling a serial ADC in a portable handheld application. This document provides an explanation of the VHDL code for the CoolRunner CPLD.

This application note describes the use of a Xilinx CoolRunner™ XPLA3 CPLD to implement a NAND Flash memory interface. CoolRunner CPLDs are the lowest power CPLD available and the ideal target device for memory interface applications.

This document details the VHDL implementation of an system Management Bus (SMBus) controller in a Xilinx CoolRunner™ XPLA3 256-macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an SMBus controller.

This application note provides an introduction to the capabilities and functionality of the User Constraint File (UCF) for CoolRunner™ XPLA3 CPLD designs in WebPACK™ Project Navigator.

This document details the VHDL implementation of an 8051 microcontroller interface in a Xilinx® CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making these CPLDs the perfect interface devices for many of today’s popular microcontrollers.

This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master.

This application note describes system design techniques using a low power CoolRunner™ CPLD to reduce overall system power consumption. Utilizing a CoolRunner CPLD to offload operations from the system microprocessor keeps the processor in a power saving mode longer and contributes to significant power savings.

This document details specific implementation techniques which may be used to decrease power consumption in CPLD designs.

This application note illustrates the implementation of an IrDA and UART system using a CoolRunner™ XPLA3 CPLD. The note also describes the fundamental building blocks required to create a half-duplex IrDA and full-duplex UART interface design.

This document provides a brief description of how to perform ISP operations with XPLA3 CPLDs.

This document describes the features and benefits of the I/O cells provided by Xilinx® CoolRunner™ XPLA3 CPLDs.

This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144 and XCR3128XL CPLDs. This note also discusses the functionality of the UART.

This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder and discusses the reasons to use Manchester code. The code can be compiled into either the Xilinx XC9572 or XCR3064XL CPLD.

This document details the VHDL implementation of a fibre channel byte-oriented transmission encoder and decoder in a Xilinx® CoolRunner™ CPLD. CoolRunner CPLDs are the lowest power CPLDs available today and can be utilized in any network design where reliable point-to-point transceivers are required. CoolRunner CPLDs utilize the patented Fast Zero Power (FZP) design technique to simultaneously deliver high performance and low power consumption. These devices offer pin-to-pin delays of 5.0 ns, and less than 100 µA of standby current (approximately 1/3 of the power consumed by other competing CPLDs at fMAX ).

This document describes the macrocell configurations of Xilinx® CoolRunner™ XPLA CPLDs.

This document highlights the advantages of utilizing the universal control terms provided in the CoolRunner™ XPLA3 CPLD architecture. This application note also discusses design examples showing the efficiency of these universal control terms.

This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner XPLA3 256 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an I2C controller.

This document provides a description of the CMOS output structures of the CoolRunner™ CPLDs and details some advantages of using true CMOS (rail-to-rail capable) output drivers.

This application note describes how to enter timing constraints for CPLDs, and how to verify that your timing contraints have been met.

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

100% Material Data Declaration Sheet (Pb-free PLCC)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for VQ100 package

Design File(s):

• IPC-1752 Form

VQG44 - Material Declaration Data Sheet (Pb-free VQFP)

Design File(s):

• IPC-1752 Form

VQG100 - Material Declaration Data Sheet (Pb-free VQFP)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for VQ44 package

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

This White Paper shows a method for calculating how much TTL logic can be fit on a Xilinx CPLD.

This document describes how to use the CoolRunner XPLA3 timing model.

This document gives a detailed description of the CoolRunner XPLA3 clocking options.

This white paper describes the CoolRunner™ XPLA3 CPLD architecture.