Device User Guides

This guide describes the RocketIO™ GTX transceivers available in the Virtex®-5 TXT and FXT devices.

This guide describes the Virtex®-5 FPGA RocketIO™ Transceiver Signal Integrity Simulation (SIS) Kit for Synopsys HSPICE.

This guide provides information on PCB design for Virtex®-5 devices, with a focus on strategies for making design decisions at the PCB and the interface level.

This document describes the behavior of the I/Os under various operating conditions. It describes how to use the different termination modes, how to understand thresholds, and how loading affects the I/Os.

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bit-stream encryption, Boundary-Scan and JTAG configuration, and reconfiguration techniques.

Describes the configuration features of the Spartan®-3 Generation FPGAs. Includes the Spartan-3A, Spartan-3AN, Spartan-3A DSP, Spartan-3E, and Spartan-3 FPGA families.

The Platform Flash PROM User Guide describes advanced features of the Platform Flash PROM family of devices. This guide also includes information on configuration setups, generation of the files used to program this PROM family, and other design considerations.

This guide provides complete packing information for Virtex®-4 QPro™-V (QV) Radiation-Hardened FPGAs in 1.00-mm pitch ceramic flip-chip column grid array (CF) packages. Virtex-4 QV Radiation Hardened FPGAs are offered exclusively in ceramic flip-chip column grid array (CF) packages that are optimally designed for improved thermal cycle reliability.

Design File(s):

• UG 496 Virtex-4 QV pinout CSV file

This user guide provides an overview of the Xilinx Video Over IP system.

This contains reference systems for the Spartan®-3A DSP 3SD1800A MicroBlaze™ Reference Systems

Design File(s):

• MicroBlaze Processor Kit Reference Systems
• Design file for UG486

This guide describes the functionality of the dedicated Integrated Endpoint block for PCI Express® designs available in the Virtex®-5 LXT, SXT, TXT, and FXT devices.

This guide describes the RocketIO™ GTP transceivers available in the Virtex®-5 LXT and SXT devices.

This guide describes the Platform Flash XL feature set, demonstrates the common configuration mode setups supported, and provides the software flows necessary to generate the programming files and indirectly program the device in-system.

This signal integrity simulation kit provides a simulation environment for users to evaluate their channel designs with the Virtex®-5 FPGA RocketIO™ GTX transceivers. This document explains how to use the examples provided in the design kit and helps users modify them for their own needs.

This guide describes the Embedded Tri-Mode Ethernet Media Access Controller (MAC) available in the Virtex®-4 FX family.

This signal integrity simulation kit provides a simulation environment for users to evaluate their channel designs with the Virtex-5 FPGA RocketIO GTP transceivers. This document explains how to use the examples provided in the design kit and helps users modify them for their own needs.

This guide provides information about how to use the Video Starter Kit (VSK) to begin experimenting with video processing using the Spartan®-3A DSP family of FPGAs.

The Virtex®-5 FPGA User Guide includes chapters on clocking resources, clock management technology, phase-locked loops, block RAM, Configurable Logic Blocks (CLBs), SelectIO™ resources, and SelectIO logic resources.

Design File(s):

• ug190_SSO_Calculator.zip

This document describes the Virtex®-5 FPGA DSP48E slice.

Design File(s):

• ug193.zip

Functional description of the Spartan®-3 generation FPGA architecture and how to use it. Includes the Spartan-3A, Spartan-3AN, Spartan-3A DSP, Spartan-3E, and Spartan-3 platforms.

This all-encompassing configuration guide includes detailed information on the Virtex®-5 FPGA configuration interfaces (JTAG, Serial, SelectMAP, SPI and BPI), and it discusses flows and techniques for bitstream encryption, readback and reconfiguration.

This document discusses thermal, electrical, moisture, and soldering characteristics of Xilinx® device packages.

This document provides complete packaging information for the radiation-hardened Virtex®-5QV FPGA in a 1.00 mm pitch ceramic flip-chip column grid array CF1752 package. The package is optimally designed for improved thermal cycle reliability.

This document describes the features and operation of the HW-CLK-101-SCLK2 SuperClock-2 module. The SuperClock-2 module is a plug-in board that provides a programmable, low-noise and low-jitter clock source for Xilinx transceiver characterization boards

This user guide provides Virtex®-5 device pinouts, package specifications, pinout diagrams, PCB design rules, and thermal data.

This guide describes the System Monitor functionality available in all Virtex®-5 devices.

Design File(s):

• ug192.zip

This reference guide describes the embedded processor block available in the Virtex®-5 FXT device.

This User Guide describes the XPower Estimator (XPE), a power estimation tool used in the predesign and preimplementation phases of a design to be implemented in a Xilinx FPGA. XPE works with Microsoft Excel.

The Virtex®-6 FPGA GTX Transceiver Signal Integrity Simulation Kit for Synopsys HSPICE enables signal integrity simulations of a communication link between Virtex-6 FPGA GTX transceivers. This kit includes models of the line driver of the transmitter and the analog front end of the receiver of the GTX transceivers.

This guide describes the Virtex®-6 FPGA GTX Transceiver Signal Integrity Simulation (SIS) Kit for Mentor Graphics HyperLynx.

This guide describes the GTH transceivers available in the Virtex®-6 HXT FPGAs.

This guide describes the System Monitor functionality.

This guide describes the DSP48E1 slice in Virtex®-6 FPGAs and includes configuration examples.

This guide describes the dedicated tri-mode Ethernet media access controller (TEMAC) available in all the Virtex®-6 FPGAs except the XC6VLX760.

This guide describes the GTX transceivers available in all the Virtex®-6 FPGAs except the XC6VLX760.

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Virtex®-6 devices.

This guide describes the clocking resources available in all the Virtex®-6 devices, including the MMCM and Clock Buffers.

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques for Virtex®-6 FPGAs.

This guide describes the SelectIO™ resources available in all the Virtex®-6 devices.

This guide describes the function and operation of the Spartan®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This document contains information about the AXI4 version of the core.

The Spartan®-6 FPGA GTP Transceiver Signal Integrity Simulation (SIS) Kit for Mentor Graphics HyperLynx provides a simulation environment for evaluating channel designs for Spartan-6 FPGA GTP transceivers. This document describes how to install the SIS kit and get started with simulations.

This guide describes the DSP48A1 slice available in Spartan®-6 FPGAs.

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

This user guide provides information on the various hardware methods of power management in Spartan®-6 FPGAs, primarily focusing on the suspend mode.

This guide provides information on PCB design for Spartan®-6 devices, with a focus on strategies for making decisions at the PCB and the interface level.

This guide describes the SelectIO™ resources available in all Spartan®-6 FPGAs.

This guide describes the Spartan®-6 FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs to the most popular memory standards.

This guide describes the usage and implementation of the GTP transceivers available in the Spartan®-6 LXT FPGAs.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Spartan®-6 FPGAs.

This document describes how to migrate designs utilizing prior FPGA architectures to 7 series FPGAs for improved density (cost), performance, and power.

This guide describes the GTX transceivers available in the Kintex™-7 FPGAs.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Xilinx® 7 series FPGAs.

This guide serves as a technical reference describing the Xilinx® 7 series FPGAs XADC, a dual 12-bit, 1 MSPS analog-to-digital converter with on-chip sensors.

Design File(s):

• Design file for UG480

This guide describes the DSP48E1 slice in 7 Series FPGAs and includes configuration examples.

This guide provides information on PCB design and pin planning for 7 series FPGAs, with a focus on strategies for making design decisions at the PCB and interface level.

This all-encompassing configuration guide includes chapters on configuration interfaces, multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques for Xilinx® 7 series FPGAs.

This guide describes the 7 Series FPGAs block RAM and FIFO capabilities.

This guide describes the Virtex®-6 device block RAM and FIFO capabilities.

Summary of the reliability test data and results for Xilinx devices updated four times per year.

This guide describes the clocking resources available in all Spartan®-6 FPGAs, including the DCMs and PLLs.

This guide describes the Spartan®-6 FPGA block RAM capabilities.

This guide serves as a technical reference describing the 7 series FPGAs clocking resources.

This guide describes the SelectIO™ resources available in the 7 series FPGAs.

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

This user guide is a detailed functional description of XtremeDSP™ Solution Spartan®-3A DSP technology.

This guide explains how to install the Xilinx® family of USB programming cables, including information related to installing Xilinx USB cables with ISE® and WebPACK™ software.

Design File(s):

• ug344_windows.zip
• install_drivers.tar.gz

For Spartan®-3AN FPGA applications that read or write data to or from the In-System Flash memory after configuration.

The Virtex™-4 RocketIO Bit Error Rate Tester (XBERT) Reference Design for the ML42x development platforms demonstrates a serial link between two or more Virtex-4 RocketIO Multi-Gigabit Transceiver (MGT) ports embedded within a single Virtex-4 FPGA. This user guide provides instructions to set up and operate the XBERT reference design on the ML421, ML423, ML424 and ML425 platforms.

This user guide provides instructions for setting up and operating the RocketIO™ X BERT reference design on MK322 and MK325 platforms.

The reference design described in this document serves as an introduction to Xilinx embedded solutions, specifically the PowerPC™ processor. It also covers the Xilinx Platform Studio™ tool and the included Base System Builder™ wizard. Finally, this reference design illustrates how to add custom or third-party IP to the PowerPC APU interface.

The Virtex®-4 RocketIO™ Multi-Gigabit Transceiver User Guide provides the product designer with the detailed technical information needed to successfully implement the RocketIO Multi-Gigabit Transceiver in Virtex-4 designs.

This guide describes Virtex®-4 device pinouts and package specifications; it also includes pinout diagrams and thermal data.

The guide describes the XtremeDSP™ slice and includes reference designs for using the DSP48 math functions and various FIR filters.

Design File(s):

• ug073_c02.zip
• ug073_c03.zip
• ug073_c04.zip
• ug073_c05.zip
• ug073_c06.zip
• ug073_c07.zip

This guide describes the PCB guidelines for the Virtex®-4 family. It covers SelectIO™ interface signaling, RocketIO™ transceiver signaling, power distribution systems, PCB breakout, and parts placement.

The Virtex®-4 FPGA User Guide includes chapters on Clocking Resources, Digital Clock Manager (DCM), Phase-Matched Clock Dividers (PMCD), Block RAM and FIFO memory, Configurable Logic Blocks (CLBs), SelectIO™ resources, and SelectIO logic resources.

Design File(s):

• ug070.zip

The RocketIO BERT reference design for ML32x platforms demonstrates a 2.5 Gbps to 3.125 Gbps serial link between two RocketIO multi-gigabit transceiver (MGT) ports, embedded within a single Virtex-II Pro FPGA. This product is not recommended for new designs.

RocketIO™ X transceivers with flexible, programmable features allow a multi-gigabit serial transceiver (MGT) to be easily integrated into any Virtex-II Pro™ X design. This product is obsolete/under obsolescence.

This user guide discusses managing hardware and software data with Virtex-II Pro devices as well as Virtex-II Pro wake-up solutions. This product is not recommended for new designs.

This User Guide provides a general overview as well as digital design considerations, analog design considerations, simulation and implementation options, timing model, valid data/control characters, and RocketIO-related online publications. This product is not recommended for new designs.

This document contains information about Timing Models, Design Considerations, Configuration, PCB Design Considerations, BitGen and PROMGen Switches, and XC18V00 Series PROMs. This product is not recommended for new designs.

Design File(s):

• ppcverilog_template.zip
• ppcvhdl_template.zip
• xc2vp_verilog.zip
• xc2vp_vhdl.zip