XC9500

The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns.

The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles.

Data Sheet for 288 Macrocell In-System Programmable CPLD

Data Sheet for 216 Macrocell 5V In-System Programmable CPLD

The XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns.

Data Sheet for 72 macrocell 5V programmable CPLD

Data Sheet for 36 Macrocell 5V Programmable CPLD

This document describes the behavior of the I/Os under various operating conditions. It describes how to use the different termination modes, how to understand thresholds, and how loading affects the I/Os.

This document discusses thermal, electrical, moisture, and soldering characteristics of Xilinx® device packages.

Summary of the reliability test data and results for Xilinx devices updated four times per year.

Xilinx is implementing a Warehouse Management System (WMS) in its internal warehouses worldwide. As a result, a license plate number (LPN), which is a unique tracking number, will now appear on labels beginning in August 2007. There are no changes to the form, fit, or function of the product.

The purpose of this notice is to announce the addition of STATS ChipPAC in Singapore (SCS) as a qualified assembly partner for Plastic Quad Flat Pack (PQFP), Thin Quad Flat Pack (TQFP/VQFP), and Ball Grid Array in wire bond (BGA) packages.

Design File(s):

• Qualification Report for XCN06016

This notification describes a material set consolidation of mold compound and die-attach epoxy across various packages in all Xilinx device families. The new material set is already used in Xilinx RoHS-compliant products. There is no change to the form, fit, or function of the devices.

Design File(s):

• Qualification Report for XCN05011

Xilinx is changing from a 6 dot HIC to a 3 dot HIC to comply with industry standard dry packing requirements, JEDEC standard J-STD-033.

Xilinx is changing the primary supplier for Ball Grid Array (BGA) shipping trays from Peak to both Daewon and Kostat.

To advice customers that Xilinx has added alternate shipping tray for 28mm x 28mm QFP packages and 31mm x 31mm BGA packages.

This notice describes the latest additions for obsolescence and should be considered in conjunction with previous discontinuance notices produced by Xilinx.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate that Xilinx is discontinuing certain XC1700, XC4000E, XC4000XLA, XC5200, Spartan®-IIE, Spartan-3AN, Virtex®, Virtex-E, Virtex-II, CPLD and Aerospace & Defense “XQ” products.

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

To communicate that Xilinx is discontinuing Spartan®-XL FPGA, XC9500 In-System Programmable CPLD products, all Automotive IQ Family offerings of Spartan®-II FPGA products and CoolRunner™ XPLA3 CPLD products.

This application note describes how to drive LEDs using Xilinx CPLDs.

Mixed signal systems require logic parts that can operate with two power supplies. XC9500™ CPLDs are designed to operate in either mixed 5V/3.3V systems or 5V-only systems. To handle both conditions, care has been taken to ensure that designers need not introduce elaborate circuitry to guarantee that 5V and 3.3V power supplies rise or fall in any particular sequence. This application note describes the underlying XC9500 circuitry to give designers the understanding they need to best use these CPLDs.

This introduction covers the basics of VHDL as applied to CPLDs. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language to extract the best performance from CPLD designs.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

Describes the bahavior of CPLDs during power up.

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature. (For Virtex™ FPGAs, see XAPP135.) For additional data, see the Xilinx™ IBIS files.

This application note discusses XC9500XL™ device use in multi-voltage systems.

This application note covers the basics of how to use Verilog as applied to Complex Programmable Logic Devices. Various combinational logic circuit examples, such as multiplexers, decoders, encoders, comparators, and adders are provided. Synchronous logic circuit examples, such as counters and state machines are also provided.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

This application note describes how to use the XC9500™ timing model. All XC9500 CPLDs have a uniform architecture and an identical timing model, making them very easy to use and understand. To determine specific timing details, users need only compare their paths of interest to the architectural diagrams and, using the timing model presented here, perform a simple addition of incremental time delays.

This application note discusses basic design considerations for in-system programming of multiple XC9500 devices in a boundary scan chain, and shows how to design systems that contain multiple XC9500 devices as well as other IEEE 1149.1-compatible devices.

This application note explains the XC9500™ boundary scan interface and demonstrates the software available for programming and testing XC9500 CPLDs. An appendix summarizes the JTAG programmer operations and surveys the additional operations supported by XC9500 CPLDs for in-system programming.

This application note describes how to program XC9500™ devices in-system, using standard Serial Vector Format (SVF) stimulus files.

This application note describes how to enter timing constraints for CPLDs, and how to verify that your timing contraints have been met.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

Design File(s):

• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

VQG44 - Material Declaration Data Sheet (Pb-free VQFP)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for VQ44 package

Design File(s):

• IPC-1752 Form

This White Paper shows a method for calculating how much TTL logic can be fit on a Xilinx CPLD.