XC9500XL

This data sheet describes the XC9500XL 3.3V CPLD family, including architecture, basic family device descriptions, and package options.

XC95288XL 3.3V High-Performance CPLD

XC95144XL 3.3V High-Performance CPLD

XC9572XL 3.3V High-Performance CPLD

XC9536XL 3.3V High-Performance CPLD

This document describes the behavior of the I/Os under various operating conditions. It describes how to use the different termination modes, how to understand thresholds, and how loading affects the I/Os.

This document discusses thermal, electrical, moisture, and soldering characteristics of Xilinx® device packages.

Summary of the reliability test data and results for Xilinx devices updated four times per year.

Xilinx is implementing a Warehouse Management System (WMS) in its internal warehouses worldwide. As a result, a license plate number (LPN), which is a unique tracking number, will now appear on labels beginning in August 2007. There are no changes to the form, fit, or function of the product.

The purpose of this notice is to announce the addition of STATS ChipPAC in Singapore (SCS) as a qualified assembly partner for Plastic Quad Flat Pack (PQFP), Thin Quad Flat Pack (TQFP/VQFP), and Ball Grid Array in wire bond (BGA) packages.

Design File(s):

• Qualification Report for XCN06016

Xilinx is adding shipping trays produced by Kostat, Inc. for the new CS144/CSG144 and CS280/CSG280 Laminate packages.

A package substrate change for Chip Scale (Tape) and lead-free Chip Scale (Tape).

Design File(s):

• Qualification Report for XCN05018

The purpose of this notification is to communicate a change in the wafer fabrication facility for the XC95288XL and XC9536XL CPLD devices.

This notification describes a material set consolidation of mold compound and die-attach epoxy across various packages in all Xilinx device families. The new material set is already used in Xilinx RoHS-compliant products. There is no change to the form, fit, or function of the devices.

Design File(s):

• Qualification Report for XCN05011

The XC95144XL and XC9572XL CPLD devices will transition from a 0.35mm four-layer metal Flash CMOS process at UMC, Taiwan to a 0.35mm four-layer metal Flash CMOS process at He Jian Technology Company, China.

Xilinx is changing from a 6 dot HIC to a 3 dot HIC to comply with industry standard dry packing requirements, JEDEC standard J-STD-033.

This new circuit revision increases the tolerance of the configuration circuitry to non-monotonic power supply ramps and provides a more robust solution in customer applications.

Xilinx is changing the primary supplier for Ball Grid Array (BGA) shipping trays from Peak to both Daewon and Kostat.

Xilinx is discontinuing certain Spartan®, XC4000XL, CoolRunner™, and Programming Solution products.

To advice customers that Xilinx has added alternate shipping tray for 28mm x 28mm QFP packages and 31mm x 31mm BGA packages.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

This application note describes how to drive LEDs using Xilinx CPLDs.

Checklist application note giving best practice CPLD design methodology.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

Describes the bahavior of CPLDs during power up.

This application note discusses XC9500XL™ device use in multi-voltage systems.

This application note covers the basics of how to use Verilog as applied to Complex Programmable Logic Devices. Various combinational logic circuit examples, such as multiplexers, decoders, encoders, comparators, and adders are provided. Synchronous logic circuit examples, such as counters and state machines are also provided.

This application note describes how to properly configure XC9500XL CPLDs in 5V/3.3V mixed systems, 3.3V-only systems, and 3.3/2.5V mixed systems.

Discovering electrical problems during the debug stage is too late. The printed circuit board has been built and may need significant changes to debug. The best approach is to avoid problems by planning for options at the outset. This application note provides a framework for checklisting a design early to eliminate problems.

This application note discusses XC9500XL CPLD power estimation and optimization and provides designers with an understanding of sense-amplifier-based CPLD power dissipation. The note also provides a brief discussion of the process for estimation. With this information, you can accurately assess the power dissipation for a design. Guidelines that permit you to make key choices to manage the power dissipation of your design and understand the package thermal limits are also presented.

This application note helps designers get the best results from XC9500XL™ CPLDs. Included are practical details on such topics as pin migration, timing, mixed voltage interfacing, power management, PCB layout, high speed considerations and JTAG best practices.

This application note describes the use of the XC9500XL™ timing model.

This introduction covers the basics of VHDL as applied to CPLDs. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language to extract the best performance from CPLD designs.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

This application note discusses basic design considerations for in-system programming of multiple XC9500 devices in a boundary scan chain, and shows how to design systems that contain multiple XC9500 devices as well as other IEEE 1149.1-compatible devices.

This application note explains the XC9500™ boundary scan interface and demonstrates the software available for programming and testing XC9500 CPLDs. An appendix summarizes the JTAG programmer operations and surveys the additional operations supported by XC9500 CPLDs for in-system programming.

This application note describes how to program XC9500™ devices in-system, using standard Serial Vector Format (SVF) stimulus files.

This application note describes how to enter timing constraints for CPLDs, and how to verify that your timing contraints have been met.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

This application note documents using a Xilinx® CPLD as a motor controller.

Design File(s):

• xapp940.zip

This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages.

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

100% Material Data Declaration Sheet (Pb-free PLCC)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for VQ64 package

Design File(s):

• IPC-1752 Form

VQG44 - Material Declaration Data Sheet (Pb-free VQFP)

Design File(s):

• IPC-1752 Form

VQG64 - Material Declaration Data Sheet (Pb-free VQFP)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for VQ44 package

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

This White Paper shows a method for calculating how much TTL logic can be fit on a Xilinx CPLD.

White Paper on the advantages and cost savings of using Xilinx CPLDs instead of 7400 Discrete Devices.